Meenakshi Garg

WORK HISTORY

EDUCATION

SKILLS

ABOUT MEENAKSHI GARG

21+ Years of Experience in Digital IC Domain.Leading sign-off team to meet needs of customers on advanced technology nodes.Driving advanced technology nodes in the era of complex chips and Stacked Die. 3DIC, D2D sign off for big chips having 2B Inst.Leading Tape-outs efforts for lower tech nodes - N2/3 SF2/SF2PLeading advanced technologies like Aging, EMIR, Variation and Robustness analysis etc.Driving advanced approach to high frequency clock planning and sign off to maximize PPA with integrity and jitter analysis.Working with customers to handle complexity of big SoC chips through advanced features like HG, Corner reduction, HS and HT on SF2/N3/N2.Hands-On expertise on advanced features on PrimeTime, PrimePower, PrimeShield, Jitter and Clock Integrity.Driving advanced technologies for PPA push Vt Skew/ ISA.Driving timing convergence on complex designs with next generation ECO solution PrimeClosure.Worked as Timing Methodology Engineer at Global Foundries Inc.Worked as Staff Timing Methodology Engineer at Qualcomm.Worked as Senior Principal Product Engineer at Cadence Design System Pvt. Ltd. on Timing Signoff and Physical Aware ECO Tool.Key leadership skills- Product Management- Managing multiple Prime* products - Getting Concepts to implementation working as a bridge between customer and RnD organization.Project Management- Working with different LoB at customer, managing the issues in well defined way is the key to success for both customer and project. Time management, criticality assessment, positioning are my key responsibilities.Resource management, Mentorship.Strategic initiatives and planning.Leading technology initiatives across multiple customers.Key technical expertise area - Timing, Variation, Aging, LLE, Timing and Clock ECO, Clock Jitter, Clock integrity, VT Skew and Interconnect Skew variation analysis, EMIR, Power.