Mark Jervis

Product Definition @Altera

Marlow, GB
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Jan 2025 — Present

Product Definition @Altera

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Marlow, GB

Holistic planning lead for hardware, software and IP for the complete hard processor subsystems and soft-core processors across Altera\'s FPGAs. Also responsible for functional safety planning. The role requires translating market intelligence plus strategic direction into technical requirements for existing and future products, with staged rolled outs and monitored execution across multiple engineering teams.

EDUCATION

1989 — 1992

University of Bristol

Bachelor’s Degree, Mathematics

1987 — 1989

Kingston College

Four A levels, Maths, Further Maths, Physics, Chemistry

1992 — 1996

University of Bristol

Doctor of Philosophy (PhD), Mathematics

1982 — 1987

Teddington School

Eleven O-Levels & OA-levels, Maths, Maths OA, Eng. Lang., Eng. Lit., Stats, Economics, Art, DT, Physics, Chemistry, Geography.

N/A

Imperial Business School

Master of Business Administration - MBA, Business, Management, Marketing, and Related Support Services

SKILLS

C++System DesignSocSemiconductorsAlgorithmsVerilogCEmbedded SystemsEdaApplication-Specific Integrated Circuits (Asic)ModelsimHardware ArchitectureVhdlHigh Level SynthesisRtl CodingDigital Signal ProcessingRtl DesignAlteraDebuggingFpga

ABOUT MARK JERVIS

Adaptable math PhD & MBA driving holistic tech lifecycle impact

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Mark Jervis — Product Definition at Altera in Marlow, GB | Unifers