Manju Kiran Subbarayappa

WORK HISTORY

EDUCATION

SKILLS

ABOUT MANJU KIRAN SUBBARAYAPPA

Experience in Physical IC design, Logic Synthesis, Formal comparison, Formal Verification, Physical synthesis,Floor planning, Power Planning, Power grid, Place/Route, Clock Tree Synthesis,RC Extraction, Physical Verification\'s like DRC, LVS, ERC•Familier with different ASIC Design flows form RTL to GDSII.•Expertise in design optimization, static timing analysis, gate & switch level simulation, signal integrity check•Knowledge of Memory structures SRAM(SYNC(Flow through, Pipelined,Burst)),DRAM, Regfile•Good knowledge and understanding of Computer Architecture.•Hands-on experience in SOC,ASIC, FPGA design & Verification.•Experience in RTL (Verilog, VHDL, and System Verilog) coding.•Good knowledge of DFT,BIST/BILBO structures for combined signature analysis and scan technique •Good knowledge of verification methodologies like OVM, RVM, UVM developed upon VMM.•Good experience in computer programming languages like C, C++, Python,Java and Assembly language.•Knowledge of scripting Languages like Shell, Perl, Tcl.•Strong communication skills, both written and verbal communication.•Expertise in software(object) oriented physical design using python.• Knowledge of physical design algorithms•Knowledge of Interoperable PCell Library produced by Ciranova (Synopsys acquired), and Ciranova\'s stand alone utility Program called Cngenlib which convert python parametric cell design to open access library format.EDA Tools:Cadence & Synopsys tool chain Virtuoso,Assura,Calibre,RTL compiler,Soc Encounter,Design Compiler,Formality,Prime time,IC compiler,Embed-it(virage logic memory compiler),NanoTime. VCS,Modelsim,Spectre,Hspice,NanoSim,Pycell StudioSoftware Development Tools:Wing ware IDE,Easy Eclipse,Eclipse,Ciranova\'s Pyros,Wing IDEPhysical Design API\'s: Ciranova\'s Python API, GdsMill