Manisha Sharma
Lead Sta Engineer @Cadence
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WORK HISTORY
Lead Sta Engineer @Cadence
Bengaluru, IN
Technology : N2P & N3EComplexity : Tempus flow development, Certus deployment, SPEF correlation, Timing correlation between PNR & SignoffTool-set : Tempus, Innovus, CertusRoles and Responsibilities- Developed Tempus STA flows with PGV enabled to handle big subsystems- Certus enablement and achieving a good fix rate post implementation in PD- N2 correlation activities which included SPEF correlation and timing correlation for SOD- Worked on various aspects of correlation in terms of derates, constraints, TDRC and coverage of the design between the various signoff tools
EDUCATION
Kendriya Vidyalaya
12th, Physicschemistry Maths
Hitam Hyderabad Institute of Technology and Management
Engineers Degree, Electrical Electronics and Communications Engineering
ABOUT MANISHA SHARMA
Aiming to be proficient in complete ASIC design flow and to continue adapting the lower node challenges by exercising my skills and experience towards professional growth. Working experience in process nodes N2P, N3E, 3LPE, 4FF, 5LPE, 10nm, 16nm and 28nm. Good knowledge in Floorplanning, place, CTS and STA. Familiar with Synthesis, contraints building and pre-layout STA. Hands on experience on TCL scripting. Experience - Having 7 years of experience in VLSI implementation (STA, PD). Working experience with clients such as Google, Qualcomm and Intel.
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