Konin Calliste Koua
Lead Design Engineer @Cadence
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WORK HISTORY
Lead Design Engineer @Cadence
CA
Analog & Mixed Signal Layout DesignDeep sub-micron CMOS nodes: FinFet 14nm, 10nm and 7nm
EDUCATION
Classe Préparatoires au Grandes écoles Mohamed V (Beni-Mellal, Maroc)
Concours des Grandes Écoles d'Ingénieurs, Maths Sup, Physiques et Sciences de l'ingénieur
Stanford Continuing Studies
An Introduction to Programming: Python
ENSICAEN - Ecole Nationale Supérieure d'Ingénieurs de Caen
Ingénieur en Électronique
Université de Sherbrooke
M.s.A, Integrated Circuit Design
Stanford Continuing Studies
Agile Management: A hands-on introduction to product development
Stanford Continuing Studies
Project Management: Practices and Tools
LYCEE SCIENTIFIQUE DE YAMOUSSOUKRO
Bac C (Série Scientifique)
SKILLS
ABOUT KONIN CALLISTE KOUA
Circuit design, layout, simulation and experimental measurement- CMOS technologies: TSMC 180nm, IBM 130nm, GF 65nm, TSMC 65nm, ST 28nm, TSMC 16nm and 10nm FinFet - Analog/Mixed-Signal IC design and layout - Low noise design and measurement - Design and layout of Digital-to-Analog Converters - High Speed SERDES IP Layout Design - High performance PHY Layout Design (DDR Interface.)EDA Tools- Cadence Design and verification tools - Mentor Graphics verification tools(Calibre LVS and DRC)- Tanner EDA(S-Edit, L-Edit)- EM/IR Verification Electrical Engineer, member of the Association of Professional Engineers of Quebec (OIQ)Skills in : Analog/Mixed-Signal Integrated Circuit Design (Design, Layout, Verification, Parasitics extraction), Low Noise Design, ASIC Integration and Layout Floorplanning,Frontend design for Medical Imaging, High performance SERDES IP, multi-site work
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