Karna Kumar Durga Manohar
Vlsi Deisgn and Verification Trainee @Vlsiguru Training Institute
Signup · Get unlimited contacts
WORK HISTORY
Vlsi Deisgn and Verification Trainee @Vlsiguru Training Institute
Trained on advanced design and verification concepts, built UVM verification environments from scratch for various hardware modules. Worked on various sequences, sequencers and writing tests in the UVM environment. • Contributed to the creation of comprehensive test plans and development of UVCs for APB and AHB protocols. • Explored and applied strategies to optimize test cases and enhance functional coverage efficiency.• Debugged RTL and testbench code using schematic tracing and RTL signal tracing, identified and fixed coding issues.• Trained on Design-for-test (DFT) techniques, executed full scan insertion on 17k+ flip-flop block, resolved DRC violations, and conducted ATPG simulations under both timing and no-timing aware scenarios.
EDUCATION
University College of Engineering, Vizianagaram
Bachelor of Technology - BTech, Electrical and Electronics Engineering
ZPHS Vetapalem
10th Class
Portland State University
Master's degree, Electrical and computer engineering
Portland State University
Master of Science - MS, Electrical and Computer Engineering
Sri Chaitanya College of Education
Intermediate, MPC
ABOUT KARNA KUMAR DURGA MANOHAR
Aspiring Silicon Engineer with a strong foundation in Hardware Design and Design Verification, skilled in designing hardware circuits using System Verilog/Verilog and verifying them through testbenches, Universal Verification Methodology (UVM), and formal verification techniques. I have successfully designed numerous hardware logic modules and verified the majority of them. My expertise includes developing hardware logic designs, implementing advanced verification techniques, creating verification constraints, developing functional coverage modules, and crafting robust assertions for formal verification. With in-depth knowledge of Computer Architecture, I excel in designing and verifying critical hardware components such as FIFOs, 5-stage pipelines, memories, and caches. My graduate projects highlight a wide range of experience in hardware design and verification, including the design and verification of an Asynchronous FIFO using direct, random, and constrained random stimulus, implementing a Split L1 Cache, simulating a DDR5 Memory Controller, performing branch prediction analysis, and verifying the I2C protocol. These projects have equipped me with practical skills in building and validating complex hardware systems. I am actively seeking internships and full-time opportunities in Design Verification, Validation, RTL Design, and Computer Architecture roles. I am eager to contribute to impactful projects while further enhancing my skills and knowledge in these fields.
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.