Rakesh Gogula

WORK HISTORY

EDUCATION

ABOUT RAKESH GOGULA

I am an Entry-Level VLSI Design and Verification Engineer with a strong foundation in digital logic design, HDL programming, and functional verification. I hold a B.Tech degree in Electronics and Communication Engineering with hands-on experience in Verilog and SystemVerilog.I have worked on design and verification of digital blocks including memory and FIFO architectures, where I developed testbenches, assertions, and functional coverage models. I am familiar with core UVM concepts and have experience using industry-standard simulators such as QuestaSim and ModelSim.My academic and project work also includes the design and analysis of approximate multipliers using FinFET technology, with a focus on power, delay, and energy efficiency. This work was presented at 2025 and published in the Xplore digital library.I am actively seeking entry-level opportunities in VLSI Design or Verification where I can contribute to verifying robust digital systems and grow within the semiconductor industry.