John Jekel
Ip Rtl Design Engineering Internship @Altera
Waterloo, ON, CA
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WORK HISTORY
Sep 2025 — Present
Ip Rtl Design Engineering Internship @Altera
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Toronto, ON, CA
Used SystemRDL to implement registers for a new Ethernet AN/LT IP, targeting an upcoming Altera FPGA- Actively investigating and developing AXI and Avalon arbiters, decoders, and bridges for use in the IP- This internship is still ongoing, so there\'s more to come as the term progresses.
EDUCATION
2026
University of Waterloo
Bachelor of Applied Science - BASc, Computer Engineering
2017 — 2021
Cardinal Carter Catholic Secondary School
High School Diploma, High School
ABOUT JOHN JEKEL
I am a fourth-year Computer Engineering student at the University of Waterloo on my last…
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