Johan Bastiaens
Sr Hardware Layout Manager @Altera
San Francisco, CA, US
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WORK HISTORY
Jan 2025 — Present
Sr Hardware Layout Manager @Altera
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San Jose, CA, US
Managing a team of layout designers on leading FPGA designs at Altera, an Intel Company.Managing analog IP\'s such as ADC, DLL, ESD designs and others, as well as IP\'s based upon standard cells and clock trees.Workflow and methodology enhancements to ensure quality and always on time milestone delivery.
SKILLS
Application-Specific Integrated Circuits (Asic)Physical VerificationSemiconductorsPeople SkillsTeam LeadershipPerlEdaAnalogMicroprocessorsDrcTeam ManagementLayout ManagerLvsCadenceIcMask Design ManagerPhysical DesignChild Mental HealthProcessorsCmosProject ManagementMentorMentoring New HiresPhysical Design Verification (Pdv)VlsiAsicCircuit DesignVery-Large-Scale Integration (Vlsi)DebuggingSocYouth Mentoring
ABOUT JOHAN BASTIAENS
Experienced leader with broad background in physical design (IO, SerDes, PLL, SRAM, ASIC,…
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