Jaehyup Kim
Principal Engineer @Marvell Technology
San Jose, CA, US
EMAILS
j••••••••@marvell.com
MOBILE NUMBERS
+16•••••••33
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WORK HISTORY
May 2019 — Present
Principal Engineer @Marvell Technology
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Santa Clara, US
EDUCATION
1999 — 2001
Korea Advanced Institute of Science and Technology
MS, Electrical Engineering
2007 — 2012
University of Minnesota
Doctor of Philosophy (Ph.D.), Electrical, Electronics and Communications Engineering
1995 — 1999
Korea University
BS, Electronic Engineering
SKILLS
IcSimulinkHardwareAsicPllSystems DesignSemiconductorsVerilogIntegrated Circuit DesignLabviewDigital Signal ProcessorsAnalog Circuit DesignCmosIntegrated Circuits (Ic)Pcb DesignSimulationDspAnalogCadence VirtuosoVlsiRfSimulationsMatlabSocMixed SignalCircuit Design
ABOUT JAEHYUP KIM
Designed PLL/DLL/MDLL and DDR PHY LVDS TX/RX for 4+ years in Qualcomm Designed CMOS Transceiver for biomedical applicationDesigned RF Fractional-N PLL synthesizer for WiBro/WiMaxSystem modeling and analysis skill with aid of MATLAB/Simulink/Mathcad/Cadence/Verilog-AMS Various work experiences on from IC design to hardware system design
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