Gonzalo Pacheco

Hardware Engineer @NI (National Instruments)

More than eight years of experience in design of RTL development with VHDL on data acquisition I/O firmware to be deployed onto FPGA, which communicates with measurement devices via SPI. Experience with FPGAs including Kintex, Virtex and Zynq programmable devices. Currently working on a vertical team developing new features for customers from HDL to user-visible API in C#. Responsibilities: • Product Owner of CompactRIO driver. • RTL architecture design, development, test, and verification. • Developed component-level and system-level test benches. • Work on automated tools in LabVIEW to help with testing and debugging. • Owner of multiple Test Suites to ensure adequate coverage for the product. • Solved synchronization challenges among devices from different product families. • Managed project timeline and facilitated the design validation/verification effort of new product line with several measurement devices. • Review and Creation and of technical documentation. • Scrum Master for a team of 12 developers. • Mentor junior engineers and interns.