Ellandula Mahesh
Lead Design Engineer @Cadence
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WORK HISTORY
Lead Design Engineer @Cadence
Hyderabad, IN
EDUCATION
Geethanjali College of Engineering and Technology
Master of Technology, VLSI- System Design
Gurunanak Institute of Technical Campus
Batcholar of technology , Electronics and communications engineering
ABOUT ELLANDULA MAHESH
Worked on Multiple IP\'s as a Lead engineer like ADC\'s, DAC\'s, SerDes\'s, DDR, PLL\'s, of multiple Bit rate, Architecture & speed\'s (20GHz, 16GHz, 8Gsps & more) Image sensor (256*256 pixels), MEM\'s sensor Interface. Worked on Multiple block\'s as a team member like CML Drivers, MDAC\'s, OTA\'s (multiple architectures), Bandgap reference circuits, Voltage regulators (1.8V, 1.2V), Comparators, Power on reset (POR), Biasing circuit, 3-bit flash ADC, I/O pads with ESD structures & Standard cell library development.Hands on devices tape out expertise in Triplewell, Bulk CMOS, FD-SOI & FinFet devices. Hands on experience with technology nodes like 2nm, 3nm, 7nm, 12nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm, 110nm & 180nm for foundries GF, ON-Semi, X-FAB, TSMC, Tower Jazz & INTEL18A.Managing layout from issues like EM, IR, Shielding, latch-up, Deep N-well, Well proximity, LOD, STI, Antenna effect. & PEX Iterations.Verification capabilities (DRC, LVS, ERC, DFM & PEX) using Calibre, Pegasus, & Assura.Extensive knowledge of matching such as common centroid, interleaving, proximity.Good knowledge of CMOS concepts & Basic electronics.
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