Shubham Tayal
Layout Design, Staff Engineer @Synopsys Inc
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WORK HISTORY
Layout Design, Staff Engineer @Synopsys Inc
Hyderabad, IN
EDUCATION
YMCA University of Science & Technology, Faridabad
Master’s Degree, VLSI Design
Vaish College of Engineering, Rohtak
Engineer’s Degree, Electrical, Electronics and Communications Engineering
National Institute of Technology Kurukshetra
Doctor of Philosophy (Ph.D.), Device Modelling
ABOUT SHUBHAM TAYAL
I am a Standard Cell Layout Engineer with 8+ years of combined experience in the semiconductor industry and academia, including 3+ years focused on advanced node standard cell layout and library development (TSMC N3C/N2, N2P, N3E, N3P, N4P, Intel 18A). My expertise lies in designing, optimizing, and validating standard cell libraries with strong PPA (power, performance, area) characteristics while ensuring LVS/DRC compliance.At Synopsys, I have contributed as a Layout Lead/PoC for multiple advanced nodes, where I developed custom automation utilities to accelerate and improve design quality:Cell-Level Area Improvement Utility (ICV coding) – identifies optimization opportunities.PG Locator Utility (ICV coding) – visualizes PG connectivity at cell level for debug/reliability checks.Layout QoR Utility (Python/Bash) – benchmarks internal standard cell libraries in terms of area and higher-metal usage.I bring a solid understanding of layout-dependent effects (LDEs: LOD, WPE, OSE) and their impact on circuit performance, along with mentoring experience to support team productivity and high-quality project delivery.Recognized with the Synopsys ACE Award for Innovation and backed by a strong research foundation (50+ publications, 10+ edited books), I combine practical layout engineering expertise with a research-driven mindset. I am always open to connecting with professionals in VLSI, semiconductor design, and EDA to explore opportunities in standard cell layout and library development.
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