David Salomoni
Senior Engineer Technology Development @GlobalFoundries
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WORK HISTORY
Senior Engineer Technology Development @GlobalFoundries
Dresden, DE
Drive FEOL process integration for advanced technology platforms, defining process windows for critical modules (Spacer, Gate CD) to meet device performance and variability targets. Execute DOE-based experiments (JMP, D3) to study CD sensitivity, corner behavior, and process interactions, supporting mobility optimization and robust scaling. Perform SPC, Cpk, and inline data analytics to monitor process stability, identify drift and excursion signatures, and drive yield and performance improvements. Correlate inline metrology (CD, TEM, WET) with electrical performance, supporting corner analysis and root-cause identification for FEOL variability issues. Apply Lean Six Sigma methodologies (DMAIC, 8D, FMEA mindset) for structured problem-solving, cross-module debug, and continuous process optimization. Previously supported BEOL NVM (STT-MRAM) integration on 300 mm manufacturing lines, including process monitoring, robustness improvement, and PCP definition for high-volume manufacturing.
EDUCATION
Università degli Studi di Torino
Bachelor's degree in Physics
Politecnico di Torino
Master's degree, Nanotechnologies for ICTs
Grenoble INP - UGA
Doctor of Philosophy - PhD, Nano-Physics
ABOUT DAVID SALOMONI
Technology Development & Integration Engineer | PhD Nanophysics | Advanced Semiconductor ManufacturingI work on process integration and device performance in advanced semiconductor technologies, bridging physics, manufacturing, and data-driven decision making.Currently at GlobalFoundries, I support Technology Development on 300 mm lines. My work spans from BEOL STT-MRAM integration (etch, liner, encapsulation, retention analysis, MTJ stack tuning, inline PCP definition) to FEOL RF-SOI integration, with a strong focus on Spacer and Gate CD control, mobility optimization, and process stability.I spend most of my time:running lots, and DOE (JMP) into actionable process decisionscorrelating inline metrology with electrical performance (dcube)supporting cross-module debug and 8D investigations to close performance or yield gapsI’m Lean Six Sigma Yellow Belt certified (Green Belt in progress) and enjoy structured problem solving where data, integration constraints, and manufacturing reality meet.Before industry, I completed a PhD at CEA-Grenoble / SPINTEC, working on spintronics and nanofabrication, with publications in Nature Communications and Physical Review Applied. That research background still shapes how I approach engineering today: hypothesis-driven, quantitative, and pragmatic.Happy to connect with people working in advanced nodes, RF technologies, emerging memories, or semiconductor manufacturing at scale.
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