Daniele di Pasquali

Digital Verification Engineer @NXP Semiconductors

Sant\'Agata li Battiati, IT

As a skilled Digital Verification Engineer with over four years of experience in IP and SoC verification, I have successfully contributed to the FW Verification of full-chip designs for SoCs with ARM CPUs and various peripherals, such as, GPIO, ADC,AHB, APB, SPI, SPMI, USB, and more.My expertise spans UVM, SystemVerilog, Python, Firmware Verification, and Formal Verification.Key Achievements & Contributions- Formal Methodology and Tool Optimization- JG A2D Verification Methodology Development- UVM RAL Model Implementation- Project Success & Timely Tapeout Completion- SOC Validation and Firmware Debug.Technical Expertise- Languages & Methodologies: UVM, SystemVerilog, Python- Verification Focus: Functional Verification, Formal Verification, FW Verification - Key Tools & Technologies: Cadence JasperGold, Cadence vManager/IMC, Magilem, Python Scripting

Università degli Studi di Palermo

Laurea triennale, Ingegneria elettronica

Università degli Studi di Palermo

Laurea Magistrale LM, Ingegneria elettronica