Bhanu Kiran Kuchalakanti
Principal Design Engineer @Cadence
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WORK HISTORY
Principal Design Engineer @Cadence
Bangalore, IN
EDUCATION
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
ABOUT BHANU KIRAN KUCHALAKANTI
Responsible for DDRIO /GDDR IO/ SERDES/ ADC/SOUNDWIRE MIPI/D-PHY MIPI IP Layout Development: • Development of standard and complex IO layout in different FINFET and CMOS technologies. • Development of layout of BANDGAP references, PVT compensation, Resistor calibration, TX and RX Macros in different technologies and Connectivity IP. • Ensuring Quality and Successful delivery of Custom Layouts with Efficiency. Encouraging the designers to incorporate the innovative Ideas in the designs. • Understanding the system level application of IOs. Defining the Layout Implementation and verification strategy of IOs for complex system level integration. Responsible for DDRIO /GDDR IO/ SERDES IP Design Reviews and Layout and Verification Solutions: • Conducting the design review of different IO blocks and complete IO buffer PLL, RX and TX. • Providing innovative flows and SKILL scripts to improve Quality and Efficiency of Design flows. • Providing innovative solutions to solve the IO /SERDES Execution and verification problems by scripts related problems. Responsible for Handling IP delivery flow and GDSII delivery for Chip Integration teams/Foundry • Verifying the Quality of Backend collaterals, through in house custom tools based on python 4. Responsible for training/mentoring to the Layout designers: Conducting technical sessions on Analog Layout design and Circuit design of Bandgap. • Conducting one-one training sessions with fresh graduates. • Conducting knowledge sharing sessions on Layout Design Major Projects Undertaken: • Responsible for Managing and implementation of IP layout /Test chip support SOUND WIRE MIPI IP in intel 3nm Process. • Responsible for Managing and evaluation of SF2 Samsung process.• Responsible for Managing and implementation DDRIO layout development in TSMC 5nm, SAMSUNG 7nm.• Responsible for SAR ADC layout development in TSMC 7nm,5nm,3nm • Responsible for GDDRIO TX IP and ILL layout development in TSMC 5nm, SAMSUNG 7nm.• Design of Layout of PLL in TSMC 7nm, FDSOI 28nm.
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