Aruj Mistry
Lead Design Engineer @Cadence
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WORK HISTORY
Lead Design Engineer @Cadence
Bengaluru, IN
EDUCATION
Indian Institute of Technology, Kharagpur
M.TECH, microelectronics and vlsi design
HINDU SCHOOL
SECONDARY-2010 HIGHER SECONDARY-2102, SCIENCE
Indian Institute of Engineering Science and Technology (IIEST), Shibpur
B.E., ELECTRONICS AND TELECOMMUNICATION
ABOUT ARUJ MISTRY
3 years of experience in post silicon validation and characterization of USB Type C SOC Device.•Development of Characterization/Test plan in Analog,Mixed signal and digital block on SoC Device.•Automating Bench setup using python based Automation.•Work with cross functional teams for quick resolution during silicon bring up.•Post Silicon Characterization/Validation.E-mail- a••••••••@gmail.comcontact number-98••••••32
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