Abdul Rafay
Principal Design Verification Engineer @Astera Labs
Mississauga, ON, CA
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WORK HISTORY
Apr 2022 — Present
Principal Design Verification Engineer @Astera Labs
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CXL 2.0 product features verification planning, execution, debug, and coverage - Ownership of the complete PCIe DV of Gen6 Retimer chip, from product definition to tape out, and planning for post-Si. Successfully delivered on schedule for Gen6 functionality on the MPW
EDUCATION
2008 — 2011
NED University of Engineering and Technology
BE, Electronics
2016 — 2018
University of Calgary
Master’s Degree, Electrical and Computer Engineering
2000 — 2005
St. Michael's Convent
GCE O Level, Pre-Eng
2005 — 2007
The Fahims School System
GCE A Level, Pre-Eng
ABOUT ABDUL RAFAY
Industrial experience in development of embedded systems, ASIC/FPGA IP Cores and…
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