Zuoguo Wu
- Role
- Universal Chiplet Interconnect Express (Ucie) at Universal Chiplet Interconnect Express Ucie
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Zuoguo Wu
I am currently a Senior Principal Engineer and Manager of an IO Circuits and Architecture…
Experience
Universal Chiplet Interconnect Express (Ucie)
Universal Chiplet Interconnect Express Ucie
Present
Skills
- Computer Architecture
- Spectre
- Spice
- Vlsi
- High Speed Interfaces
- Usb
- Formal Verification
- Mixed Signal
- Rf Circuits
- Circuit Design
- Firmware
- Silicon
- Very-Large-Scale Integration (Vlsi)
- Fpga
- Asic
- Pll
- Hardware Architecture
- Dft
- Modelsim
- Power Management
- Vhdl
- Simulations
- Intel
- Digital Signal Processors
- Analog Circuit Design
- Soc
- I/O
- Logic Design
- Tcl
- Analog
- Semiconductors
- Functional Verification
- Integrated Circuit Design
- Microprocessors
- Cadence
- Ic
- Systemverilog
- Embedded Systems
- Eda
- Processors
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