Zili Fang
Verification Engineer @Silicon Labs
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WORK HISTORY
Verification Engineer @Silicon Labs
IP & subsystem functional and formal verificationExplore and actively adapt AI into daily workflow. Published one DVCON paper on AI-accelerated workflow
EDUCATION
Texas A&M University
Master's Degree, Computer Engineering
University of Electronic Science and Technology of China
Bachelor's Degree, Microelectronics Science and Engineering
ABOUT ZILI FANG
Design Verification Engineer with 5 years of experience verifying IPs mainly using SystemVerilog and UVM, currently at Silicon Labs. I work on both functional and formal verification, building clean, reusable environments and partnering closely with design teams to catch issues early. I’m also interested in exploring how AI and automation can improve verification workflows, from test generation to debug and productivity.
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