Zhouning Zhang
- Role
- Senior Asic Design Engineer at NVIDIA
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Zhouning Zhang
Self-motivated and quick learner
Experience
Senior Asic Design Engineer
Jan 2023 — Present
Skills
- Stateflow
- Verilog
- Algorithm
- Python
- Cadence Virtuoso
- Perl
- Application-Specific Integrated Circuits (Asic)
- Field-Programmable Gate Arrays (Fpga)
- Rtl Coding
- Very-Large-Scale Integration (Vlsi)
- C
- C++
- Ncsim
- Modelsim
- Xilinx Vivado
- Cadence Encounter
- Design Compiler
- Rtl Design
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