Zhen Song

About Zhen Song

Hands-on experience in FPGA/ASIC logic synthesis, verification, simulation, timing closure, P&R and hardware bring-up. Work experience of defining RTL block level specifications Proficient in Verilog RTL coding for blocks Experience with C/C++, Python, Java Experience with protocols such as Interlaken, USB 4, DDR 4, Serdes, I2C,PCIe and DSP Experience with code quality tools, such as Spyglass lint tool Good familiarity with automation and scripting languages such as Python, Perl and TCL Familiar with EDA tools such as VCS, ModelSim, Vivado and Quartus II Support verification teams by participating in test plan development and verification coverage definition

Experience

1. Principal Software Engineer

   Cadence

   Aug 2022 — Present · Austin, TX, US

   Support of application and product engineers for customer problems and requests, including problem analysis, debugging, and development of new features in C/C++ enhance synthesis results with respect to timing, area and power. Modify RTL to improve area and timing and test on newly developed synthesis software. Validation and analysis on benchmark designs to measure achieved improvements.

Education

• University of Arkansas

  Master's, Digital Circuits and Design

  2009 — 2011

• University of Electronic Science and Technology of China (UESTC)

  Bachelor, Electrical Engineering

  2004 — 2008