Zhaojun Liu
Asic Physical Design Engineer @NVIDIA
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WORK HISTORY
Asic Physical Design Engineer @NVIDIA
Santa Clara, CA, US
EDUCATION
Tianjin Normal University
Bachelor of Applied Science - BASc, Science and Technology of Electronic Information
University of Rochester
Master's degree, Electrical Engineering
SKILLS
ABOUT ZHAOJUN LIU
3.5+ year hands-on experience with more than 20 successful tapeouts of mix-signal SoC/digital IP design and verification including Synthesis, Physical Design(PD), Static Timing Analysis(STA) and Timing Closure, Physical Design Verification(PDV), and Logical Equivalence Check(LEC).• Build up from scratch of PD/STA/PDV flow automations using Tcl/Shell, which results in significant turnaround time improvement and consistently exceeding original project targets in terms of chip reliability and tapeout dates.• Experience in Low Power Design and implementation technique, knowledge of UPF.• Proficiency with Unix-based Cadence Innovus/Encounter/Virtuoso/Voltus/Conformal, Calibre/Assura, Synopsys Design Compiler and PrimeTime. • Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation.
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