Zezhou Liu
IC Packaging Engineer at Apple | PhD in Theoretical and Applied Mechanics at Cornell | MS in Electrical Engineering at Purdue (ongoing)
- Role
- Ic Packaging Simulation Engineer at Apple
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
Experience
Ic Packaging Simulation Engineer
Jul 2021 — Present · Cupertino, CA, US
Semiconductor IC packaging mechanical FEM simulations• Modeling includes warpage, solder joint reliability (SJR), chip-package interaction (CPI), shock test, thermal cycling (TC) test, FT/SLT/SoC station/heatsink installation, and system tip test• Majority focus is on Apple Silicon Mx Ultra Chip.Theoretical framework development for IC packagingMethodology development for large size SoC package
Education
Tsinghua University
Master of Science - MS
2013 — 2016
Tongji University
Bachelor of Engineering - BE
2009 — 2013
Cornell University
Doctor of Philosophy - PhD
2016 — 2021
Purdue University
Master of Science - MS
2024 — 2029
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