Zeyu Bu
Design Verification Engineer at Meta
- Role
- Design Verification Engineer at Meta
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Dec 2025 — Present · San Francisco, CA, US
Education
University of Michigan
Master of Science (MS), VLSI @ DIGITAL CIRCUIT DESIGN
2014 — 2016
Shanghai Jiao Tong University
Bachelor of Science (BS), Electrical and Electronics Engineering
2010 — 2014
Skills
- Circuit Physical Design
- Labview
- Electrical Engineering
- Matlab
- C++
- Java
- Verilog
- Embedded Systems
- Cadence Virtuoso
- Vhdl
- Cadence
- Circuit Synthesis and Optimization
- Nc-Verilog
- Systemverilog
- Sql
- Linux
- C
- Programming
- Computer Architecture
- Simulink
- Vlsi
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