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Zeeshan Ahmad

TestChip Physical Design | Memory layout | Analog Layout

Role
Staff Engineer at STMicroelectronics
Location
South Delhi, DL, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

About Zeeshan Ahmad

4 years of Experience in Physical Design & Verification of Test chips…

Experience

  1. Staff Engineer

    STMicroelectronics

    Apr 2024 — Present · Noida, IN

Education

  • City Montessori School, Lucknow

    Highschool

    2001 — 2006

  • Jamia Millia Islamia

    Bachelor's degree

    2008 — 2012

  • Unity college, lucknow

    Intermediate

    2006 — 2008

Skills

  • C
  • Windows
  • Microprocessors
  • English
  • C++
  • Vhdl
  • Memory Layout
  • Vlsi
  • Matlab
  • Html
  • Embedded Systems
  • Very-Large-Scale Integration (Vlsi)
  • Pspice
  • Sram
  • Cadence Virtuoso
  • Tcl
  • Physical Design

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