Yuvapreethi G.

About Yuvapreethi G.

Design Engineer with experience in Logic Design and Verification. RTL Design and RDL for Hardware Data Accelerator IPs at Intel. Formal Verification, Assertion-based verification. Strong knowledge of writing architectural register definition in RDLSkill Set:• Front end : RTL Design, Simulation, Verification. • Programming Languages : System Verilog, UVM, RDL, Verilog, SVA, Perl• Tools : JasperGold, FEV, Synopsys VCS, OneSource, Nebulon

Experience

1. Ip Logic Design Engineer

   Intel

   Nov 2016 — Present

   Responsible for writing architectural register definition in RDL and to implement the underlying design integration.• Proficient in register tool flows such as Onesource, Nebulon, and Critter which allows RDL definition to be used in auto-generating IP design and validation collateral.• RDL experience in handling the configuration and MMIO registers and integration with RTL.• Responsible for development of RTL design to target power, performance and area.• Wide knowledge of setting up debugging and resolving RTL issues with front-end tools and experience with perl/makefile/xml for automating multiple tool flows.• Performed verification planning and execution with focus on advanced analysis techniques - formal verification (model checking), assertion-based verification.• Experience with the implementation of ECOs, netlist debug and cadence conformal for proving design equivalence.• Member of the front-end design team working on the PCIe IP – involved in formally verifying the LTSSM block in the physical layer.

Education

• University of Minnesota

  Master of Science (M.S.), Electrical and Electronics Engineering

  2013 — 2015

• Franklin High School, WI

  High School Diploma

  2006 — 2009

• John F. Kennedy High School

  High School

  2005 — 2006

• SRM IST Chennai

  Bachelor of Technology (B.Tech.), Electronics and Communication Engineering

  2009 — 2013

Skills

• C
• Amba
• Spice
• Embedded C
• Very-Large-Scale Integration (Vlsi)
• Spyglass Txv
• Simulink
• Spyglass
• Application-Specific Integrated Circuits (Asic)
• C++
• Pcie
• Python
• Functional Verification
• Assertion Based Verification
• Microprocessors
• Jaspergold Formal Verification
• Verilog
• Pspice
• Microcontrollers
• Vhdl
• Strategic Planning
• Linux
• Modelsim
• Rtl Design
• Formal Verification
• Matlab
• Conformal Lec
• Xilinx Ise
• Team Management
• Arm Architecture
• Team Leadership
• Perl
• Embedded Systems
• Cadence Virtuoso
• Vlsi
• Systemverilog
• Java
• Universal Verification Methodology (Uvm)