Yury Audzevich
Principal Engineer @Arm
Cambridge, GB
EMAILS
MOBILE NUMBERS
+91 *********19
Signup · Get unlimited contacts
WORK HISTORY
Apr 2025 — Present
Principal Engineer @Arm
View department →
Cambridgeshire, GB
Memory Subsystem Architecture definition and design role: includes architectural planning, performance, efficiency and reliability tuning, and optimizing of the memory hierarchy for the latest generation of Arm\'s systems.
EDUCATION
2000 — 2005
Belarusian State University
Specialist degree, Radio Physics and Electronics
2006 — 2010
Università di Trento
Doctor of Philosophy (Ph.D.), Telecommunications Engineering
SKILLS
Software DevelopmentPythonLatexPcb EngineeringSynopsys ToolsC++Field-Programmable Gate Arrays (Fpga)FpgaAsicSoftware EngineeringIntegrated Circuit DesignHigh Speed InterfacesLinuxModelsimSignal ProcessingPcieDebuggingOptical CommunicationsApplication-Specific Integrated Circuits (Asic)AlgorithmsXilinxSystemverilogUniversal Verification Methodology (Uvm)Rtl DesignEthernetSemiconductorsVhdlSimulationsVerilogCEnergy Efficiency
ABOUT YURY AUDZEVICH
Principal Engineer at Arm | ex University of Cambridge | PhD
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.