About Yunwu Zhao
SOC design across different technology node, familiar with SOC low power design flow and…
Experience
Present
Education
Nankai University
Bachelor, Engineering
1997 — 2001
Skills
- Timing Closure
- Verilog
- Microcontrollers
- Power Intent File Development
- Cmos
- Soc
- Asic
- Mixed Signal
- Lec / Clp
- Logic Synthesis
- Timing Sign Off
- Configuration Management
- Management
- Project Management
- Eda
- Physical Design
- Rtl Design
- Static Timing Analysis
- Low-Power Design
- Ic
- Semiconductors
- Integrated Circuit Design
- Systemverilog
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.