Jack

Intern @Analog Devices

Tempe, AZ, US
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

May 2025 — Present

Intern @Analog Devices

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Boston, MA, US

EDUCATION

2024 — 2026

Ira A. Fulton Schools of Engineering at Arizona State University

Master of Science - MS

2014 — 2018

Yuan-Ze University

Bachelor of Engineering - BE

ABOUT JACK

Authorized to work in USA w/o sponsorship. An Electrical Engineering graduate student with a strong foundation in digital design and circuit analysis for technology nodes (3nm, 5nm, 8nm). Experienced in the Electronic Design Automation (EDA) field. Extensive experience in new feature testing and research & development. Proficient in handling SOC designs and possessing good knowledge of PNR flow (Cadence/Innovus), timing concepts (Synopsys/PrimeTime), and physical verification (Siemens EDA/Calibre).

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