Yu Fen Huang
Design Engineer @ Cadence | Ex-DRAM Engineer Intern @ Micron | MS ECE @ UMich
- Role
- Design Engineer Ii at Cadence
- Location
- Ann Arbor, MI, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Engineer Ii
Nov 2024 — Present · San Jose, CA, US
Education
University of Michigan
Master of Science - MS, Electrical and Computer Engineering
National Taiwan University
Bachelor's degree, Engineering Science and Ocean Engineering
National Taiwan University
學士, Engineering Science and Ocean Engineering
2018 — 2022
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