Yoshi Yamamoto
Sr Principal Dft Engineer @Ampere
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WORK HISTORY
Sr Principal Dft Engineer @Ampere
Santa Clara County, CA, US
EDUCATION
The University of Electro-Communications
Bachelor's degree, Physics
SKILLS
ABOUT YOSHI YAMAMOTO
I am a hardware/software engineering manager specialized in developing semi-custom semiconductor design and the design methodology for high performance application. In my career, I have- Strong leadership for design implementation and design methodology, especially DFT, logic synthesis, timing analysis and etc- Deep technical knowledge about DFT, scan compress, memory bist, jtag, ijtag, logic bist, hierarchal DFT and IP tests (Serdes, PCIe, DDR and etc.)- Managed the engineering team and collaborated with oversea internal/external teams to achieve the project goals- Accomplished 5+ projects. The latest project was 28nm enterprise application project- Assumed a hand-on role as needed for tool execution, analysis, finding solutions to meet goalsSpecialtyASIC/ASSP design from multiple hand-offs thru production release phaseDFTLogic SynthesisTiming analysis and closure Equivalence checkPlace and routeIP integrationProject ManagementMethodology DevelopmentC/C++, perl, tcl, python, ruby, javaUNIX/Linux
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