Yong-Fong Lee

About Yong-Fong Lee

Professional Experiences and Interests • Software and hardware system performance and scalability • Compiler optimization and program analysis • Runtime systems such as Java Virtual Machine and Binary Translator • Graph-theoretic algorithm design Patents and Publications • 9 patents issued • 7 journal articles • 13 conference papers

Experience

1. Engineering Director and Principal Engineer

   Intel

   Jul 1995 — Present · Santa Clara, CA, US

   October – Present • Led a team of Intel engineers in collaboration with Oracle on Cloud, Database, AI, Analytics, and Java VM. The Intel/Oracle engineering collaboration has been highlighted as a great win-win success by both companies’ executives over the years. • Contributed to optimizing Oracle software on Intel hardware. Performance and scalability optimization work covers Oracle software products, Linux OS, and Intel platforms. Scalability optimization has been instrumental in enabling Oracle software to fully utilize Intel CPUs with ever-increasing core counts. • Drove Intel’s new architectural and platform features into Oracle products to realize their benefits for end customers (e.g, Persistent Memory and new instructions) • Collaborated with Intel architects and Oracle developers to explore architectural and platform innovations. Forward looking collaboration has had significant impacts on both Intel and Oracle products. • Provided technical and strategic input for Intel executives to engage with Oracle • Demonstrated excellent skills in leadership, mentoring, and management. Scored top marks as a manager company-wide for years. • (2014 – 2015) One-year assignment of leading a team to design and implement binary translation technologies, and explore their applications to various domains such as security. 2017 – Present • Led a team of Intel engineers working on open-source relational databases (MySQL, MariaDB, and PostgreSQL) to ensure that they are secured, high-performance, and reliable on Intel platforms July 1995 – October • Researched, designed, and implemented compiler optimization for instruction level parallelism (ILP) on the Itanium/IA-64 architecture • Contributed to designing a new Itanium micro-architecture through compiler optimization and performance simulation work • Characterized IA-64 architectural features such as data speculation and predicated execution on the first generation of Itanium processor

Education

• Rutgers, The State University of New Jersey-New Brunswick

  Doctor of Philosophy (Ph.D.), Computer Science

• National Taiwan University

  B.S., Computer Science and Information Engineering