Yong Tang
Senior Analog Design Engineer at Yangtze Memory Technologies
- Role
- Senior Analog Design Engineer at Yangtze Memory Technologies
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Yong Tang
Cadence tool simulate and layout, verification including LVS and DRC• Matlab (Simulink) model and simulation, Magic Layout, HSPICE; Testing: probe station• CMOS, BICMOS process• Operational amplifier, Compensation technology for Stability, PLL, Power management: LDO, DC-DC Converter
Experience
Senior Analog Design Engineer
Feb 2020 — Present · San Jose, CA, US
Education
Oklahoma State University
Master of Science (MS), Analog Design
2009 — 2012
Southwest Jiaotong University
B.S, Electrical Engineering
2003
Oklahoma State University
M.S, Electrical Engineering
Skills
- Verilog
- Power Management
- Cadence Virtuoso
- Matlab
- Low-Power Design
- Pcb Design
- Analog
- Spice
- Pll
- Ic
- Bicmos
- Cmos
- Analog Circuit Design
- Labview
- Amplifiers
- Circuit Design
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.