Yogitha Shamsunder

About Yogitha Shamsunder

I am Yogitha Shamsunder, a recent graduate from California State University, Long Beach, with a Master’s degree in Electrical Engineering, specializing in VLSI Design. I am currently working as a PDK Layout Engineer at Western Semiconductor, and I also worked as an Analog Layout Design Engineer at Intel Corporation. With knowledge and experience in the back-end layout concepts, like floorplanning, place and route, DRC and LVS checks - I am looking forward to channel my knowledge and enthusiasm into real-world projects. Armed with an undergraduate degree from India in Electronics and Telecommunication, and an internship as an FPGA Engineer intern, along with my Master\'s degree, my academic journey has provided me with a solid foundation in electrical engineering principles, establishing the platform for specializing in design. While I bring no formal work experience, my enthusiasm and dedication to learning are boundless.My goal is to contribute my fresh perspectives and to apply my theoretical understanding to practical applications within the industry. Transitioning from India to the vibrant academic environment at CSULB has enriched my perspective and refined my ability to collaborate across cultures. I\'m excited about the potential to engage with experienced professionals and applying my theoretical knowledge in a practical s••••••••@gmail.com |+15•••••••35

Experience

1. Semiconductor Tapeout Support Engineer

   Imec Usa

   Feb 2026 — Present · West Lafayette, IN, US

Education

• SIT- Symbiosis Institute of Technology

  Bachelor of Technology - BTech, Electronics and Telecommunication Engineering

• Gokuldham High School

  High School Diploma

  2015

• California State University, Long Beach

  Master of Science - MS, Electrical Engineering