Yogi Patil
Silicon Design Engineer at AMD. SoC Low power design and verification at AMD
- Role
- Senior Silicon Design Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Yogi Patil
I am silicon design engineer at AMD.•Power Aware simulation on UPF compilations,elaboration,•I primarily work in UPF design, Generations and verification. •I also work on synposys tool like VC- LP on Synthesised Netlist side of upf for static power check i.e Power rated Checks on IPs,Full chip. Full chip checks.•Syntax and schematics •Structural Checks•Functional Checks •Corruption • UPF consistency check with RTL design•Component Integration•TCL and Perl scripting•AMBA protocols•Isolation Control design•IP wise Power domain, Resets on SoC•Component integration on SoC
Experience
Senior Silicon Design Engineer
Dec 2025 — Present · Hyderabad, IN
Education
Shri Guru Gobind Singhji Institute of Engineering and Technology, Vishnupuri, Nanded
Bachelor's degree, Electrical, Electronic and Communications Engineering Technology/Technician
Birla Institute of Technology and Science, Pilani
Master's degree, Wireless Communication
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