Yogeshwar L.
- Role
- Soc Design Engineer - Rtl Logic at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Yogeshwar L.
I’m a NoC Design Intern at Intel and a Master\'s student in Electrical and Computer Engineering at Portland State University, specializing in digital design and computer architecture.At Intel, I work on integrating and simulating NoC subnets, automating RTL workflows, and analyzing system-level performance. I’ve also supported education as a Graduate Teaching Assistant, helping students build practical skills in Linux, Bash, and Python.With hands-on experience in RTL design, verification, and tools like SystemVerilog, UVM, and Synopsys toolchains, I’m passionate about solving real-world hardware challenges.I\'m actively seeking full-time roles in RTL design, verification, or SoC development starting June 2025.Let’s connect!
Experience
Soc Design Engineer - Rtl Logic
Oct 2025 — Present · Hillsboro, OR, US
Education
Portland State University
Master of Science - MS, Electrical and Computer Engineering
Sinhgad College of Engineering
Bachelor of Engineering - BE, Electronics and Telecommunication Engineering
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