Yogesh Singh Jadon
VLSI Enthusiast (Verilog HDL | System Verilog | UVM) | AMBA APB, AHB, AXI | SoC
- Role
- Trainee at Futurewiz
- Location
- Aligarh, IN
- LinkedIn followers
- 500 followers
About Yogesh Singh Jadon
Good knowledge of FPGA-based systems. Experienced knowledge of RTL Designing and Modeling using Verilog HDL. Experienced knowledge of System Verilog and UVM. Experienced knowledge of FPGA Synthesis and implementation tools options. Having knowledge of FPGA architecture and Design Flow. Working knowledge of Software and Hardware Debugging. Having knowledge of Digital Logic and Digital Circuit Design. Having knowledge of Technical Report Writing, Presentation and Documentation.
Experience
Trainee
Nov 2022 — Present · IN
Education
Samrat Ashok Technological Institute
Bachelor of Engineering - BE
2009 — 2013
Shri G S Institute of Technology & Science
M.E.
2016 — 2018
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