Yogesh Kumar Neela

About Yogesh Kumar Neela

MTS Silicon Design EngineerExecutive Summary- 11+ years of professional experience in the VLSI DFT domain, currently serving as DFT Lead- Led SOC-level ATPG SAF for multiple projects at Qualcomm- Owned responsibility for SOC-level ATPG pattern generation and validation, ensuring GLS tim-ing simulation signoff- Generated patterns using pattern retargeting flow with OCC implementation- Coverage top-up patterns for set/reset, CGC enable, PLL bypass mode, and coverage analysis toachieve high coverage goals- High-toggle activity patterns for stress/high temp tests- Production test pattern delivery to TE, silicon bring-up, and yield debug support for all phases un-til CS- Tester failure log diagnostics using Tessent diagnostics and low toggle shift pattern generation toaddress phasing issues- SCAN insertion for critical partitions like CPU and GPU with custom flows supporting complexpower domain designs, including low power EDT implementation- Formal verification signoff for pre and post-scan inserted netlists- Collaborated closely with the PD team to address congestion challenges, scan chain validation onintermediate/final netlists until metal tape-out, test mode constraint support, and pipeline insertionbased on timing requirements- Block-level Mbist insertion and validation with BISR- Boundary scan with 1149.1 TAP- 1687 Ijtag flow for hierarchical scan and ATPG- Hands-on experience on Industry standard EDA tools, Mentor Graphics Tessent, Cadence, Syn-opsys, VCS, NC, Verdi and LEC

Experience

1. Mts

   AMD

   Apr 2025 — Present · Hyderabad, IN

   Soc and Tile ATPG

Education

• Auroras seethaiah college of engineering

  B.Tech, Electronics and Communication Engineering

  2009 — 2013

• Sri Narayana Jr.college

  +2, Maths Physics

  2007 — 2009

Skills

• Verilog
• Logic Synthesis
• Debugging
• Dft
• Linux
• Simulations
• Perl
• System on a Chip (Soc)
• C
• Programming
• Java