Yogesh Kalbande
Google | Ex-Intel | BITS Pilani
- Role
- Senior Design Verification Lead at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Yogesh Kalbande
Experienced in ASIC Functional Verification using systemverilog and OVM/UVM methodology. Assertion and functional coverage based verification. Expert in UVM methodologies. Expert in developing test/coverage plans, from specification. Experience of multiple IP/SoC verification, advanced debugging, expertise in verilog, systemverilog. Have proven track record of delivery in fast paced, mission critical projects. Worked on Ethernet Protocols
Experience
Senior Design Verification Lead
Oct 2022 — Present · Bengaluru, IN
Education
BITS Pilani Work Integrated Learning Programmes
Master in Science (MS), Microelectronics.
2013 — 2015
Government Polytechnic, Amravati
Diploma, Electronics & Telicommunication Engineering
2005 — 2008
Government College of Engineering, Amravati.
BTECH, Electronics
2008 — 2011
Skills
- Open Verification Methodology
- Debugging
- Modelsim
- Gate Level Simulation
- Soc
- Pcie Transaction Level
- Vhdl
- C
- C++
- Engineering
- Microprocessors
- Assembly Language
- Systemverilog
- Pcie Compliant High Speed Bus Protocol
- Perl
- Embedded Systems
- Usb
- Verilog
- Vlsi
- Synopsis Vcs Simulation Tool
- Fpga
- Asic
- Functional Verification
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