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Yogeendra B N

Layout/Mask Design at Intel Corporation

Role
Layout Mask Design at Intel
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

Experience

  1. Layout Mask Design

    Intel

    May 2019 — Present

Education

  • Bangalore University

    Bachelor of Engineering

    1993 — 1997

Skills

  • Asic
  • Verilog
  • Vlsi
  • Embedded Systems
  • C
  • Soc
  • Debugging
  • Embedded Software
  • Analog Circuit Design
  • Layout Design
  • Ic
  • Mixed-Signal Ic Design
  • Semiconductors

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Yogeendra B N — Layout Mask Design at Intel in Bengaluru, KA, IN | Unifers