Yogananda Mesa
Formal verification Engineer - GPU/NPU processor at AMD
- Role
- Formal Verification Engineer - Gpu Npu Processor at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Yogananda Mesa
Experienced in Design and verification (formal and functional) with a demonstrated history of working in the semiconductor industry.Having knowledge on Digital design, Verilog, verification using Formal methodologies like property verification, Formal coverage analysis, connectivity checking, sequential equivalence and functional verification skills System Verilog and UVM.
Experience
Formal Verification Engineer - Gpu Npu Processor
Oct 2025 — Present · Hyderabad, IN
Working on verification of advanced GPU and NPU processor at AMD.contributing to design validation for next-generation high performance computing and AI acceleration technology.
Education
Jawaharlal Nehru Technological University,Anantapur
Master of Technology (MTech), vlsi system design
2014 — 2015
G. Pullla Reddy Engineering College, (Autonomous), Kurnool
Bachelor's degree, Electronics and Communication Engineering
2010 — 2013
ZPHS,Nimmanapalli
SSC
2003 — 2006
Skills
- Rtl Verification
- Functional Verification
- Ic
- System Verilog
- Integrated Circuits (Ic)
- C
- Verilog
- Formal Verification
- Vlsi
- Uvm
- Perl
- Rtl Design
- Systemverilog
- C++
- Application-Specific Integrated Circuits (Asic)
- Digital Designs
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