Ganesh Naik

About Ganesh Naik

Hardware Design and Validation Engineer with 4+ years of experience in high-speed board design, mixed-signal circuits, and system-level validation. Skilled in PCIe Gen5, USB3.x, LVDS, I2C, SPI, UART and Ethernet interfaces with expertise in power budgeting, circuit simulation and EMI/EMC compliance. Automated validation workflows to boost efficiency by 50% and resolved complex board-level issues, delivered FPGA-based designs, optimized BOMs. Passionate about bridging design and validation to ensure reliable, compliant and high-performance hardware systems

Experience

1. Electrical Validation Engineer

   NVIDIA

   Feb 2024 — Present · Bengaluru, IN

   Led comprehensive electrical validation and characterization of high-speed interfaces, including PCI Express (PCIe Gen4/Gen5), 10GBASE-T/1GBASE-T/10GT1 Ethernet, I2C, SPI, and UART, ensuring compliance with industry standards and NVIDIA’s stringent product requirements.Key responsibilities and achievementsDeveloped and executed detailed validation plans and test methodologies for high-speed serial interfaces, covering signal integrity (SI), power integrity (PI), bit error rate (BER), margining, and protocol-level compliance across multiple process, voltage, and temperature (PVT) corners.Utilized advanced lab instrumentation—high-bandwidth oscilloscopes (≥10 GHz), bit error rate testers (BERT), protocol/logic analyzers, spectrum/network analyzers, and compliance test fixtures—to perform electrical measurements, eye diagram analysis, jitter characterization, and margining for interface bring-up and validation.Executed PCIe electrical and protocol validation, including transmitter/receiver compliance, link training, equalization tuning (CTLE, DFE, FFE), lane margining, BER testing, and interoperability assessments using industry-standard tools and PCI-SIG methodologies.Performed 10GBASE-T/1GBASE-T/10GT1 Ethernet PHY validation, covering transmitter linearity, output droop, timing jitter (master/slave), power spectral density (PSD), return loss, and compliance to 802.3 standards using automated compliance suites and custom test scripts.Validated I2C, SPI, and UART interfaces at both electrical and protocol levels, measuring timing parameters (setup/hold, rise/fall times), voltage thresholds, and protocol compliance; utilized protocol analyzers and custom automation to ensure robust operation under all use cases.Drove continuous improvement of validation methodologies, introducing automation, risk-based validation, and Lean principles to reduce cycle time by 25% and enhance defect detection rates by 30%.

Education

• SDM INSTITUTE OF TECHNOLOGY (SDMIT), UJIRE

  Bachelor of Engineering - BE, Electronic and Communications Engineering Technology

  2015 — 2019