Yiyang Chen
Senior Design Verification Engineer at Iluvatar CoreX 天数智芯
- Role
- Senior Design Verification Engineer at Iluvatar CoreX 天数智芯
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Yiyang Chen
In-depth knowledge of UVM testbench, OOP programming, SystemVerilog constraints, SVA(SystemVerilog Assertions) and random stimulus generator• Solid understanding of CPU and GPU architecture with industrial experience in cache coherency protocol in multi-core processors• Proficiency in Synopsys VCS, Verdi and DVE, Cadence NCSim, RTL-Compiler, Modelsim, Xilinx ISE• Experienced in SystemVerilog, Python, Unix Shell, SystemVerilog Assertion, C++, SystemC
Experience
Senior Design Verification Engineer
Mar 2019 — Present · Shanghai City, CN
GPGPU product- Stream processor and Warp Scheduler verification lead- LLC and hub verification
Education
University of Rochester
Master's Degree, Electrical and Electronics Engineering
2012 — 2014
Xiamen University
Bachelor's Degree, Electrical and Electronics Engineering
2008 — 2012
Skills
- Cadence
- Perl
- Verilog
- C
- Fpga
- Java
- Universal Verification Methodology (Uvm)
- Matlab
- Python
- C++
- Pcb Design
- Systemverilog
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