Yeshwanth Puppala

About Yeshwanth Puppala

Sr. Power delivery validation engineer with vast experience in test, characterization, and optimization of power delivery circuits on Intel’s client products.

Experience

1. Sr Soc Debug Engineer

   Intel

   Jan 2018 — Present

   Experienced in tuning Intel client products for efficient power delivery by defining adjustments necessary to meet the target envelopes for Integrated Voltage Regulator (IVR) design specifications.• Valued by design, production testing for developing strong electrical validation strategy ensuring optimal coverage across Process corners, VF shmoo, and functional testing.• Competent in bench validation of analog device modules such as LVRs, switching converters, Digital-to-Analog Converters, Comparators, PLLs, and Bandgap reference circuits.• Analyzed power delivery network at both IP and SOC level to identify power and performance optimizations.• Calibrated IVR fault protections and communicated IP specs to key stakeholders on Intel Gen 9/10/11 processors.• Disseminated the project validation learnings and test methodologies alongside high-level product healthiness.

Education

• New Mexico State University

  Master’s Degree, Electrical, Electronics and Communications Engineering

  2012 — 2015

• Deccan College Of Engineering And Technology

  Bachelor's Degree, Electronics and Communications Engineering

  2005 — 2009

Skills

• Cmos
• Vlsi
• Analog Circuit Design
• Cadence Virtuoso
• Cadence Virtuoso Xl
• Cadence Virtuoso Layout Editor
• Linux
• Matlab
• C
• Altera Quartus
• Vhdl
• Verilog
• Analog
• Cadence
• Simulations
• Ic
• C++
• Perl
• Python
• Ltspice
• Cadence Spectre
• Cadence Analog Artist
• Cadence Icfb
• Unix
• Tcl-Tk
• Eagle Pcb
• Pcb Design