Yavika Aggarwal
SOC Verification Engineer @Samsung|| Ex-Synopsys || Ex-Cadence
- Role
- Staff Engineer at Samsung Semiconductor
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Yavika Aggarwal
Anchoring the Synopsys team as a Senior Solutions Engineer, my journey has been enriched with deep dives into USB 3.x specifications and robust customer engagement. My expertise in SystemVerilog and UVM, combined with 5 years of hands-on experience in verification engineering, has aligned seamlessly with Synopsys\'s innovative environment, allowing me to contribute to the solutions in the semiconductor industry.My academic foundation in Electronics and Communication Engineering from YMCA University underpins my expertise in digital electronics and Verilog concepts. Previously at Cadence Design Systems, I honed our skills in Verification IP R&D, focusing on USB protocol development. Our collaborative efforts resulted in notable product enhancements, fostering a customer-centric approach that leverages my proficiency. With a commitment to quality and a passion for pushing the boundaries of verification engineering, I am dedicated to delivering cutting-edge solutions.
Experience
Staff Engineer
Dec 2024 — Present · Bengaluru, IN
Education
Vivekanand Senior Secondary School,Kosli(Rewari)
Haryana Board of Secondary Education.
2001 — 2013
J.C. Bose University of Science and Technology, YMCA
Bachelor of Technology - BTech, Electronics and Communication Engineering
2015 — 2019
S.M.Arya Public School,New Delhi
All India Senior Secondary Examination
2013 — 2015
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.