Yathin Udaya Shankar Pissay
Physical Design Engineer @Intel
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WORK HISTORY
Physical Design Engineer @Intel
Fort Collins, CO, US
Physical Design tasks on Intel\'s Xeon server products• Partition level SoC design including synthesis, floorplanning, Place & Route implementation, clock & power distribution • Driving timing closure for partition and sign-off physical & electrical verification• Performing timing analysis at sub system level, triage timing issues and timing convergence for multiple corners
EDUCATION
Sir M Visvesvaraya Institute Of Technology
Bachelor’s Degree, Electronics and Communication
University at Buffalo Graduate School
Master’s Degree, Electrical Engineering
ABOUT YATHIN UDAYA SHANKAR PISSAY
Sound knowledge of Physical Design construction and analyses• Adept in Physical Design from Netlist handoff to GDS2 tape out • Good knowledge of CMOS fundamentals, Failure mechanisms, Reliability like EM/IR and Xtalk• Experience in custom Mask Design cleanup and Physical Verification• Good grasp of CMOS fabrication intricacies and process technologies• Refined planning and organizational skills with keen understanding of interdependencies• Ability to communicate clearly to accurately describe issues and follow them through for completion
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