Yaswanth Vvsn

About Yaswanth Vvsn

Technical Lead Engineer – Physical Design with 8 years of experience in ASIC/SOC implementation from RTL to GDSII across 3nm to 11nm technologies. Strong expertise in PnR flow, STA, ECOs, Timing Closure, EM/IR, and Physical Verification. Proven track record in delivering high-performance, low-power designs on aggressive schedules. Skilled in automation with TCL, Perl, and Shell scripting.

Experience

1. Senior Physical Design Engineer

   ACL Digital

   Sep 2018 — Present · San Jose, CA, US

   Overall, 8 years of work experience in physical design (VLSI).• Currently working as physical design engineer at si2chip Technologies Pvt. Ltd (an ACL Digital Company)• Comprehensive knowledge of Physical design implementation.• Hands on experience in SOC timing, TDRC and handling SOC runs using tempus, primetime.• Working knowledge on ASIC PnR flow: Floor planning, Placement, CTS, Routing, STA, and Timing Closure• Good knowledge of Signal integrity, Antenna violations, EM/IR, Low power design concepts• Hands on experience on scripting TCL, PERL, SHELL.• Good knowledge of Digital circuits, Electronic devices, CMOS circuits and Fabrication• Good communication and presentation skills.

Education

• Brindavan College of Engineering and Technology

  Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering

  2011 — 2015

Skills

• Management
• Microsoft Word
• Customer Service
• Project Management
• Microsoft Excel
• Powerpoint
• Research
• Leadership
• Public Speaking
• Microsoft Office