Yaswanth Reddy
Physical design intern @INTEL |M.TECH’26 @ MNIT Jaipur | VLSI Design |Advanced Physical Design and Verification Trainee at Maven Silicon, Bengaluru|B.Tech(ECE)
- Role
- Physical Design Intern at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Yaswanth Reddy
I\'m a VLSI enthusiast currently pursuing my M.Tech at MNIT Jaipur, with hands-on experience in physical design, RTL, and synthesis. I’ve trained and interned at Maven Silicon(Bangalore), working on real-world projects like RISC-V and ORCA using tools like Fusion Compiler, ICC2, and PrimeTime. I\'m passionate about building efficient digital systems and always eager to explore new challenges in chip design and semiconductor tech.
Experience
Physical Design Intern
Jul 2025 — Present · Bengaluru, IN
Education
Malaviya National Institute of Technology (MNIT), Jaipur
M.Tech, VLSI Design
SASI JUNIOR COLLEGE
Board of intermediate education , Mpc
Sri Vasavi Engineering College
Bachelor of Technology - BTech, Electronics and communication engineering
SASI E/M HIGH SCHOOL
Ssc
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