Yashwanth Deshini
Actively Looking for Full Time Opportunities | Master’s in Computer Engineering | VLSI Design & Verification | RTL Design | System Verilog | UVM | FPGA | ASIC | SoC Architecture |
- Role
- Design Verification Engineer at Marvell Technology
- Location
- Syracuse, NY, US
- LinkedIn followers
- 500 followers
About Yashwanth Deshini
I’m a Design Verification Engineer with a strong foundation in SystemVerilog and UVM, focused on building reliable, scalable verification environments for complex digital designs. My interests lie in coverage-driven verification, assertion-based checks, and systematic RTL debug using waveform analysis.I enjoy working close to the design, understanding protocol behavior, identifying corner cases, and translating specifications into effective test strategies. I’m particularly interested in IP-level and SoC-level verification involving standard on-chip interconnects, where correctness, robustness, and clarity of verification intent matter most.I value clean verification architecture, honest debugging, and continuous learning, and I’m motivated by environments that emphasize technical rigor, collaboration, and long-term growth in silicon design verification.
Experience
Design Verification Engineer
Jan 2025 — Present · US
Environment Support: Assisted the verification team in maintaining the PCIe/CXL verification environment by updating constraints and running existing SystemVerilog/UVM test sequences.Testbench Architecture: Architected a reusable UVM testbench from scratch, integrating ACTIVE/PASSIVE Agents, Monitors, Scoreboards, and Virtual Sequencers to support multi-master/multi-slave configurations.Coverage Closure: Assisted in developing comprehensive Functional Coverage models and cross-coverage bins, achieving 90 to 95% code and functional coverage milestones prior to tape-out.Debug Support: Supported the debugging process by tracing waveform logs in Verdi, helping to isolate 3+ timing violations in the AXI4 stream interface during stress testing.Scripting: Utilized existing Python scripts to parse log files and automate basic error reporting, reducing manual regression triage effort by approximately 30–40% and accelerating debug turnaround time.
Education
Syracuse University
Masters in computer engineering, Computer Engineering
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